There are several interrelated design parameters that must be considered during SRAM cell design. These include, for example, static noise margin (“hereinafter” SNM), write margin, bit line speed, and data retention voltage. SNM is defined as the minimum DC noise voltage necessary to flip the state of the SRAM cell. An SRAM cell can have different SNM during read and write operations, referred to as read SNM and write SNM, respectively. Read SNM is also an indicator of cell stability and is sometimes simply referred to as cell stability. A higher read SNM indicates that it is more difficult to invert the state of the cell during a read operation. Write margin is defined as the minimum bit line voltage necessary to invert the state of an SRAM cell. A higher write margin indicates that it is easier to invert the state of the cell during a write operation. Read speed is defined as the bit line slew rate in response to a high word line voltage, typically the time from the rising edge assertion of word line until some differential between the high and falling bit line is obtained. Data retention voltage is defined as the minimum power supply voltage required to retain a logic state of either “0” or “1” data in the SRAM cell in standby mode.
As process technology has scaled, it has become increasingly difficult to control the variation of transistor parameters because of a variety of sources of systemic mismatch. These sources of systemic mismatch can also include geometric sources of mismatch that arise from variation in alignment and additional lithographic effects such as corner rounding. For example, the jogs or notches in the active silicon region, used to achieve a desired ratio between the strengths of the pull-down to pass-gate transistors (represented by the width to length ratio of each of these transistors) for cell stability during a read access, can be subject to significant corner rounding. Similarly, the jogs or notches in the gate structures, used to achieve a desired pull down transistor size, can also be subject to significant corner rounding.
Threshold voltage variations become a limiting factor in transistor design as process technology is optically scaled downward while voltage cannot be similarly scaled. Threshold voltage variations between neighboring MOSFETs can have significant impact on the SNM, cell stability, write margin, read speed, and data retention voltage of the SRAM cell. Threshold voltage variations between pass-gate and pull-down transistors of the SRAM cell can degrade cell stability. During a read, the read current discharging the bit line flows through the series connection of the pass-gate and pull-down NMOS transistors. The voltage divider formed by these transistors raises the low voltage in the cell, thereby contributing to the degradation of cell stability. Variations in the threshold voltage of the pass-gate or pull-down transistor can result in a large variation in the voltage divider ratio of the pass-gate transistors to pull down transistors, increasing the likelihood of inverting the SRAM cell during a read operation, i.e., upsetting the stored state. Other SRAM cell design parameters such as write margin, bit line speed (as measured by slew rate) or read current, and data retention voltage can also be affected by threshold voltage variations.